1. Open Vivado IDE & Open Hardware Manager

Power the FPGA / SoC B’d and Connect B’d to PC, and Execute Vivado IDE.
And run “Tasks – Open Hardware Manager” to verify that the HW connection is successful before create the project.

As follows, in the case of ZYNQ SOC, Both ZYNQ PS (ARM) and PL should be recognized correctly by Vivado.

2. Create Vivado Project

Now that we have confirmed that FPGA/SOC has been recognized correctly in Vivado, we now create a Vivado project.
Once the project is created, click “Create Block Design” to create Block Design.

3. Create Block Design & Add ZYNQ7 PS IP

Type the name of Block Design as you want and click “OK”.

On the Block Diagram screen, click the “+” button and add “ZYNQ7 Processing System”.

Click “Run Block Automation” to proceed with the default settings of the ZYNQ7 PS. (Regarding Fixed I/O and DDR)

When the next screen appears, click “OK” immediately without having to configure anything else.

And connect “FCLK_CLK0” and “M_AXI_GP0_ACLK” of ZYNQ7 PS,

Double-click the ZYNQ7 PS IP to enter the IP Configuration screen.

4. DDR3 Memory Configuration

Look at the datasheet of DDR Memory used in FPGA/SOC B’d and proceed with the DDR Controller setting of ZYNQ7 PS.
(The screen below is the setting for Micron’s MT41K256M16TW-107 IT:P product.)

Configure “Training/Board Details” by checking the delay value for ACC (Address / Command Control) and each DDR ByteLane in the PCB Artwork of the FPGA/SOC B’d.

5. Bank Voltage Configuration

Check the I/O Voltage settings of Bank 0 and Bank 1 in the FPGA/SOC B’d schematic, and proceed with the appropriate Bank I/O Voltage settings in the ZYNQ7 PS IP.
(★ When Bank Voltage of ZYNQ PS is set to 1.8V, if you set 3.3V to Bank I/O Voltage, damage may occur to the FPGA/SOC.)

6. Flash Memory Configuration

Since ZYNQ-7Z010 SOMB’d is applied with Flash Memory of Quad SPI, the setting proceeds as shown in the following screen.

The QSPI clock speed setting value “133[MHz]” is based on Winbond’s “W25Q128JVEIQ” product.

7. Uart Configuration

In accordance with the UART design contents of the FPGA/SOC B’d Schematic, Carry out the UART Peripheral pin setting of the ZYNQ7 PS.

Set the Baud Rate setting of UART0/1 on the “PS-PL Configuration” tab. (Default: 115200)

8. PS MIO Configuration

To use the MIO of the ZYNQ PS, check “GPIO MIO” of “Peripheral I/O Pins” tab in the ZYNQ7 PS IP Configuration.
(If “GPIO MIO” is not enabled on Vivado’s ZYNQ PS IP, MIO control is impossible on Vitis IDE → Since it is disabled on HW)

9. PS EMIO Configuration

When you want to control the pins of the ZYNQ PL by PS, check “GPIO EMIO” and enable it,

On the “MIO Configuration” tab, set the number of EMIOs to be used.

10. Validate Block Design

When the IP configuration of the ZYNQ7 PS is complete,
① Optimize Routing
② Regenerate Layout
③ Validate Design
Click in order to visually optimize Block placement and Connection, and proceed validation of Block Design.
(The above three buttons are clicked so frequently whenever you feel boring during the design process.)

11. Create HDL Wrapper

When Block Design is completed, the corresponding Block Design must be converted to HDL.
To do this, right-click on “Block Design Name” in “Design Sources” and click “Create HDL Wrapper” as shown on the following screen.

12. Run Behavioral Simulation

To verify that the design works as intended, Carry out “Behavioural Simulation”.
(Details will be added later)

13. Run Synthesis

In order to convert the design expressed in HDL into a gate-level design, proceed Synthesis process.

You can set the number of CPU cores to use for Synthesis, but if you allocate too many CPU cores, Vivado may suddenly shut down during Synthesis due to a lack of CPU resources.
Therefore, it is recommended to set the number of CPU cores appropriately.
(When conducting this example, my PC had 16 cores and used 12 cores among them.)

Once Synthesis is completed, select “Open Synthesized Design”.

14. I/O Port Mapping

On the I/O Ports tab, set the Voltage Level and Package Pin for the entire I/O.
(I/O Port Mapping can be pre-set through the XDC file before Synthesis.)

[Note]
If any wrong design is identified on the I/O Port Mapping process, click “Open Block Design” to modify the design, and “Routing Optimization → Relegate Layout → Validate Design → Create HDL Wrapper → Run Synthesis” again.

When I/O Port Mapping is complete, press Ctrl + S with the “I/O Ports” window selected, to create a new XDC file based on that content.

As follows, it can be confirmed that a new XDC file has been created based on the contents which configured in the I/O Port Mapping process.
However, if you look at the contents of the automatically generated XDC file, you can see that semicolon(;) is missing after “set_property”. So you must add semicolon(;) to avoid synthesis error.
If you try to create a Bitstream without a semicolon(;), the corresponding I/O is not correctly mapped to pin.

After adding the semicolon(;), Synthesis needs to be proceeded again because a new XDC file was created that did not exist from a project point of view.
(For this reason, during the Block Design or HDL design step, it is efficient to complete I/O Port Mapping in advance through the XDC file.)

15. Run Implementation

When Synthesis is completed, proceed with Implementation.
(Details will be added later)

16. Generate Bitstream

When the implementation is completed, proceed with the Generate Bitstream.
(Details will be added later)

17. Export Hardware Platform File

Click “File – Export Hardware” to export the HW Platform (including Bitstream) that you just created.

Set the Hardware Platform to include Bitstream as follows.

Then, the work of the HW Engineer is all done now. (Vivado)
The SW Engineer receives the HW Platform file from the HW Engineer and designs the SW Application based on the platform.

18. Open Vitis IDE

First of all, you need to set up the workspace of the Vitis IDE.

And create a new folder which name is “Vitis” inside the Vivado project folder, and set this folder as a workspace.

Click “Create Application Project” to create a new Vitis Application Project.

Click “Next”.

Register the HW Platform file generated by Vivado.

Set the project name of the Vitis SW Application.

Click “Next” in the default setting state.

Click “Empty Application (C)”.
(In the case of Zynq, if you want to do a DDR Memory test, you can create a project with the “Zynq DRAM tests” template.)

Create a “main.c” inside the “src” folder of the application, and define the main function with empty contents as follows.
And press “Ctrl + B” to build for the Project Library and main functions.
(If the build is completed correctly, it can be determined that there is no problem with the Vitis SW Application development environment.)

Now that the Vitis SW Application development environment is confirmed to be correct,
Try to run the ZYNQ example code to turn on/off the LED with Tact SW input.

To do this, click Debug Configuration.

Double-click “Single Application Debug (GDB)” in Debug Configuration.

For each tab, click the “Debug” button to test if the example code is working correctly, without having to configure anything else.

(I checked the correct operation and confirmed that the Flash Memory Boot in the example code is also working.)