1. Create a Vivado Project for Custom AXI4-Lite IP
1. Click “Create Project” to create a new Vivado project.
Looking at it now, I think “Simple_Counter_AXI_IP_Test” would be more appropriate for the project name.
Because “Simple_Counter_AXI_IP” is created inside this project, and this project itself performs data communication tests by connecting that IP to ZYNQ PS and AXI Bus.
In any case, the IP covered in this example is “Simple Counter” AXI4-Lite IP, which receives the maximum number of clocks to be counted from the ZYNQ PS and stores it in the register.
Data communication between the ZYNQ PS and the “Simple Counter” IP takes place through the AXI4-Lite Interface.
2. Create Block Design, add and Configure the ZYNQ7 PS.
2. Create a AXI IP
1. Click “Tools – Create and Package New IP” to proceed to the IP creation & packaging stage.
2. Select “Create AXI4 Peripheral” and click “Next”.
(This option means that we will create an AXI4 IP for use in our current project.)
3. Type the name of the IP as “Simple_Counter” and click “Next”.
4. Select “Edit IP” and click “Finish”.
(For the design of logic inside IP or the addition of existing logic.)
5. Then, the IP Edit window appears as follows.
6. Now add the logic of that IP to the IP’s “Design Sources” (in this example, “simple_counter.v”)
7. Open all Verilog files where Each module in “Design Sources” is defined
8. The “Simple Counter” AXI IP’s Top Module is “Simple_Counter_v1_0” and should have a “Simple_Counter_v1_0_S00_AXI4_Lite” module as an instance inside.
And inside the “Simple_Counter_v1_0_S00_AXI4_Lite” module, the “Simple_counter” module should exist as an instance.
① Modify “Simple_Counter_v1_0_S00_AXI4_Lite” Verilog file
9. Define the port of the “Simple_Counter_v1_0_S00_AXI4_Lite” module as follows, and Create & Connect the “Simple_counter” module as an instance.
< “Simple_Counter_v1_0_S00_AXI4_Lite” module’s Port definition >
< “Simple_Counter_v1_0_S00_AXI4_Lite” module’s Signal definition used in module >
< “simple_counter” Instance creation in “Simple_Counter_v1_0_S00_AXI4_Lite” module >
② Modify “Simple_Counter_v1_0” Verilog file
10. As above, Define the port of the “Simple_Counter_v1_0” module and Connect them to the port of the “Simple_Counter_v1_0_S00_AXI4_Lite” instance.
< “Simple_Counter_v1_0” module’s Port definition >
< “Simple_Counter_v1_0_S00_AXI4_Lite” Instance’s Port modification in “Simple_Counter_v1_0” module >
11. When the Verilog file modification is complete, you can proceed the IP packaging procedure in “Package IP – Simple_Counter”.
12. In the “Identification” step, enter the information of the IP.
13. In the “Compatibility” step, set up the FPGA/SOC Family for which the IP is compatible.
14. In the “File Groups” phase, all content created and set for IP to date is created as a file (including IP driver files)
15. However, due to Xilinx’s Vivado Tool error, “Makefile” among the automatically generated files needs to be modified.
16. Open “Makefile” and copy & paste the contents of one of the files attached to this article, “Fixed_Makefile”.
17. In the “Customization Parameters” step, click “Merge changes form Customization Parameters Wizard” to update the parameters.
18. In the “Addressing and Memory” step, you can check the IP Address and Memory information.
19. In the “Customization GUI” step, you can see the GUI of the IP that has been set so far, and you can also edit this GUI.
20. Finally, in the “Review and Package” step, the IP can be packaged. (After IP packaging, a final review must be carried out.)
When you click the “Package IP” button, the IP packaging is complete and the corresponding IP creation window is closed, returning to the original project.
3. Connect the AXI IP you just created with the ZYNQ PS
1. Back to the original project, call the IP you just created to Block Design.
2. When the “Simple Counter” AXI IP is called, a “Run Connection Automation” button is created at the top.
3. When you press the “Run Connection Automation” button, the “Connection Automation” window appears as follows.
Click “OK” right away without having to configure anything else.
4. Then, the “ZYNQ PS” and “Simple Counter” IP are automatically connected to the AXI Interface.
5. Click “Optimize Routing” and “Regulate Layout” to organize the IP Blocks neatly.
6. Now, to check the “count_done” output of IP with LED, Assign it to the external pin through “Make External”.
7. Change the IP output signal “count_done” to “USER_LED1_GREEN”.
8. Create a Constaint file and assign the “USER_LED1_GREEN” Net to the “V13” pin to which the green LED on the board is connected.
9. Since all the HW settings for the “Simple Counter” IP test are completed, proceed with “Validation” for Block Design.
10. When Block Design’s “Validation” is complete, click “Create HDL Wrapper” to convert Block Design into HDL code.
11. When HDL code generation is completed, click “Generate Output Products” and proceed with Synthesis in advance in IP units.
(In the subsequent Synthesis process, only IP with changes will be Synthesized, so time saving is possible.)
12. Now proceed with the full Synthesis, and when done, review if I/O Ports are set up as we intended.
13. Proceed to the “Implementation” and “Generate Bitstream” processes, and when completed, export the Hardware Platform to create an XSA file.
4. Create SW that controls AXI IP by ZYNQ PS In Vitis SDK
1. Run Vitis and create a SW Application based on the HW Platform file (XSA) exported from Vivado.
2. Create main.c and write code as follows.
And upload the code to the board to check the actual behavior.
Then, you can visually check that the green LED on the board toggles every second, and the Max Count Value we wrote on the “Simple Counter” AXI IP is also read again and output to the serial monitor.
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Fixed_Makefile is not available