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[1] Project
1. Block Design of FIFO Generator Project
Let’s create a FIFO using FIFO Generator IP provided by Xilinx.
2. IP Configuration
(1) Basic
- FIFO Implementation ⇨ Common Clock Block RAM
1. FIFO read/write operations are performed in the same clock domain.
2. FIFO is implemented using the Block RAM resources inside the FPGA.
(2) Native Ports
- FIFO Read Mode ⇨ Standard FIFO
– After the Read Enable signal is set, the data appears on the FIFO’s Read Data. - Data Port Parameters
- Write Width ⇨ 8
Sets the write unit of the FIFO to 8 bits. - Write Depth ⇨ 1024
Configures the FIFO to store up the 1024 entries of 8-bit data (8 x 1024) - Read Width ⇨ 8
Sets the read unit of the FIFO to 8 bits.
- Write Width ⇨ 8
(3) Status Flags
(4) Data Counts
- Data Count
– Currently, the number of data entries stored in the FIFO can be checked.
(5) Summary
In the Summary, all the configuration settings of the FIFO Generator IP can be reviewed.
[2] Module & TestBench
1. Top module
2. TestBench
The following is a testbench code that writes values from 0 to 15 into the FIFO and then reads them back.
- @(posedge clk)
@(posedge clk) is a statement used to wait for the rising edge of the clock signal clk.
For important considerations when using this statement, refer to the following link: Link. - Clock Synchronization in Testbench
When designing RTL with flip-flops synchronized to a clock, non-blocking assignment (<=) is used.
Similarly, in a testbench, when providing clock-synchronized inputs to the DUT, non-blocking assignments should be used to ensure the inputs are synchronized with the clock.
If inputs are assigned using blocking assignments (=), Vivado Simulation will interpret them as level signals that are asynchronous to the clock.
[3] Simulation
1. Simulation Waveform
It can be confirmed that the values from 0 to 15 are written to the FIFO and then read back.
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