1.6K
AXI Specification of AMBA
AXI Specification of AMBA
ㅤ
1. AMBA Specification
AMBA (Advanced Microcontroller Bus Architecture) is a bus architecture designed by ARM that provides standardized interfaces for SoC design.
AMBA enables compatibility between various IP blocks within the SoC system, efficient communication, performance improvement, and low power consumption.
(Before AMBA was introduced in 1996, each IP company used proprietary interfaces, making IP compatibility very difficult.)
ㅤ
- AHB (Advanced High-Performance Bus)
A bus designed for high-performance systems, supporting high-bandwidth data transfer between memory and high-speed peripheral devices.
ㅤ - APB (Advanced Peripheral Bus)
A low-power bus used for communication with slower peripheral devices. It is simpler compared to AHB and is mainly used for tasks such as register access.
ㅤ - AXI (Advanced eXtensible Interface)
A high-performance, high-bandwidth bus designed for simultaneous data transfer between multiple masters and slaves. Key features include separate read and write data channels, QoS (Quality of Service) support, and flexible memory mapping.
ㅤ - AXI4 (Advanced eXtensible Interface 4)
An extended version of the AXI interface that provides higher performance and efficiency. It includes the following three main subsets
– AXI4: High-bandwidth, high-performance bus
– AXI4-Lite: A simple, low-bandwidth communication bus
– AXI4-Stream: A bus for data streaming
ㅤ - ACE (AXI Coherency Extensions)
Provides extensions to maintain data coherency in multicore systems.
ㅤ
- AHB (Advanced High-Performance Bus)
ㅤ
ㅤ
2. AXI4 Specification
AXI4 (Advanced eXtensible Interface 4) is part of the AMBA (Advanced Microcontroller Bus Architecture) 4.0 specification and is a high-bandwidth, low-latency bus interface used in high-performance systems.
AXI4 provides advanced features and flexibility, making it suitable for various SoC (System on Chip) designs.
ㅤ
Key Features of AXI4
- Independent Read and Write Data Channels
AXI4 handles read and write requests through independent channels, improving parallel processing performance.
ㅤ - Data Burst Transfer
AXI4 supports continuous data transfers of up to 256 bits, enhancing data transfer efficiency.
ㅤ - QoS (Quality of Service) Support
Manages the priority of data transfers to ensure the transmission of important data.
ㅤ - Support for Unaligned Address Transfers
Provides flexibility by supporting data access to unaligned addresses.
ㅤ - Register Slices
Allows the placement of register slices in the data transfer path to optimize performance.
ㅤ
- Independent Read and Write Data Channels
Components of AXI4
AXI4 interface is composed of five independent channels
- Read Address Channel
Delivers read commands to the slave, including the address and control signals for the read operation.
ㅤ - Read Data Channel
Transfers data from the slave to the master, along with status signals.
ㅤ - Write Address Channel
Delivers write commands to the slave, including the address and control signals for the write operation.
ㅤ - Write Data Channel
Transfers data from the master to the slave, along with control signals.
ㅤ - Write Response Channel
Indicates the completion status of the write operation from the slave to the master.
ㅤ
- Read Address Channel
Subsets of AXI4
AXI4 provides several subsets to meet various requirements
- AXI4
A high-bandwidth, high-performance bus interface supporting up to 256 data bits.
ㅤ - AXI4-Lite
A simple, low-bandwidth communication interface mainly used for simple tasks such as register access, supporting 32-bit data transfers.
ㅤ - AXI4-Stream
An interface designed for data streaming, suitable for packet-based data transfers. It has minimal overhead and is optimized for continuous data stream transfers.
- AXI4
ㅤ
ㅤ
3. AXI4-Lite Specification
AXI4-Lite is a simplified version of AXI4 and is part of ARM’s AMBA (Advanced Microcontroller Bus Architecture) 4.0 specification. AXI4-Lite is suitable for systems that require low-bandwidth, low-latency communication and is mainly used for simple tasks such as register access. AXI4-Lite maintains the key features of AXI4 while reducing complexity, making it easier to design and implement.
ㅤ
Key Features of AXI4-Lite
- Simplified Interface
The interface is simplified compared to AXI4, making design and implementation easier.
ㅤ - 32-bit Data Transfer
Supports data transfers with a single bit width (32 bits), enabling simple data processing.
ㅤ - Single Bit Width Address
The address bus is also fixed at 32 bits, simplifying address calculations.
ㅤ - No Burst Transfers
AXI4-Lite supports only single transfers and does not have burst transfer capability.
ㅤ - Independent Read and Write Channels
Like AXI4, it uses independent read and write channels to transfer data.
- Simplified Interface
ㅤ
Components of AXI4-Lite
AXI4-Lite is composed of five independent channels, similar to AXI4. The functions of each channel are as follows
ㅤ
- Read Address Channel
The master delivers read commands to the slave, including address and control signals.
ㅤ - Read Data Channel
The slave transfers data to the master, including data and status signals.
ㅤ - Write Address Channel
The master delivers write commands to the slave, including address and control signals.
ㅤ - Write Data Channel
The master transfers data to the slave, including data and control signals.
ㅤ - Write Response Channel
The slave indicates the completion status of the write operation to the master.
- Read Address Channel
ㅤ
Advantages of AXI4-Lite
- Simplified Design
The simple interface makes design and implementation easier.
ㅤ - Low Resource Consumption
Optimized design for low-bandwidth communication results in low resource consumption.
ㅤ - Compatibility
Complies with the AMBA standard, ensuring interoperability between various IP blocks.
ㅤ - Fewer Pins
The simplified interface reduces the number of required pins, reducing hardware complexity.
ㅤ - Efficient Register Access
Supports only single transfers, making it suitable for simple tasks such as register access.
- Simplified Design
ㅤ
Use Cases of AXI4-Lite
AXI4-Lite is mainly used in the following cases
- Register Map Access
When microcontrollers or processors access the registers of peripheral devices.
ㅤ - Low-speed Peripheral Interface
Interfaces with low-speed peripherals such as SPI and I2C.
ㅤ - Simple Data Transfer
Simple data transfer tasks that do not require high bandwidth.
- Register Map Access
ㅤ
ㅤ
4. AXI4 Communication Mechanism
AXI protocol uses the Ready/Valid Handshake mechanism.
ㅤ
Ready/Valid Handshake Mechanism
Ready/Valid Handshake consists of two main signals.
- Valid
The side that intends to send data (master or slave) activates the VALID signal along with the data. This indicates that the data is valid and ready to be transmitted. - Ready
The side that intends to receive data (slave or master) activates the READY signal. This indicates that it is ready to receive the data.
- Valid
ㅤ
Data transfer occurs when both VALID and READY signals are activated simultaneously.
Data transfer occurs in the clock cycle where both signals are active, called the handshake cycle.
ㅤ
Handshake for Each AXI Channel
AXI interface consists of five independent channels, each using the Ready/Valid Handshake mechanism.
- Read Address Channel
– ARVALID: Indicates that the master is ready to send the read address and control information.
– ARREADY: Indicates that the slave is ready to receive the read address and control information.
ㅤ - Read Data Channel
– RVALID: Indicates that the slave is ready to send the read data.
– RREADY: Indicates that the master is ready to receive the read data.
ㅤ - Write Address Channel
– AWVALID: Indicates that the master is ready to send the write address and control information.
– AWREADY: Indicates that the slave is ready to receive the write address and control information.
ㅤ - Write Data Channel
– WVALID: Indicates that the master is ready to send the write data.
– WREADY: Indicates that the slave is ready to receive the write data.
ㅤ - Write Response Channel
– BVALID: Indicates that the slave is ready to send the write response.
– BREADY: Indicates that the master is ready to receive the write response.
- Read Address Channel
ㅤ
Write Data Transfer Example
- Write Address Transfer
– AWVALID: The master activates the AWVALID signal to indicate it is ready to send the write address and control information to the slave.
– AWREADY: The slave activates the AWREADY signal to indicate it is ready to receive the write address and control information.
– Address Transfer: The write address and control information are transferred in the clock cycle when both AWVALID and AWREADY signals are activated.
ㅤ - Write Data Transfer
– WVALID: The master activates the WVALID signal to indicate it is ready to send the write data to the slave.
– WREADY: The slave activates the WREADY signal to indicate it is ready to receive the write data.
– Data Transfer: The write data is transferred in the clock cycle when both WVALID and WREADY signals are activated. This process can repeat as needed, with each transfer being part of a data burst.
ㅤ - Write Response Transfer
– BVALID: The slave activates the BVALID signal to indicate it is ready to send the write response to the master.
– BREADY: The master activates the BREADY signal to indicate it is ready to receive the write response.
– Response Transfer: The write response is transferred in the clock cycle when both BVALID and BREADY signals are activated. The response includes success or failure status.
- Write Address Transfer
ㅤ
Read Data Transfer Example
- Read Address Transfer
– ARVALID: The master activates the ARVALID signal to indicate it is ready to send the read address and control information to the slave.
– ARREADY: The slave activates the ARREADY signal to indicate it is ready to receive the read address and control information.
– Address Transfer: The read address and control information are transferred in the clock cycle when both ARVALID and ARREADY signals are activated.
ㅤ - Read Data Transfer
– RVALID: The slave activates the RVALID signal to indicate it is ready to send the read data to the master.
– RREADY: The master activates the RREADY signal to indicate it is ready to receive the read data.
– Data Transfer: The read data is transferred in the clock cycle when both RVALID and RREADY signals are activated. This process can repeat as needed, with each transfer being part of a data burst.
- Read Address Transfer
ArkX에서 더 알아보기
구독을 신청하면 최신 게시물을 이메일로 받아볼 수 있습니다.