1. Block Diagram of ZYNQ-7Z010 SOM B’d (Rev.A)
1. XC7Z010-1CLG400
This ZYNQ SoC features ARM Cortex-A9 Dual Core as Processing System (PS) and FPGA Fabric (eqv. to Artix-7) as Programmable Logic (PL).
Basic system control is performed by the PS, while the PL is utilized for hardware acceleration when computational tasks require it.
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2. DDR3L Memory
Micron’s two DDR3L Memory products (512MB) were used and connected in a fly-by-routing method to form a 1GB DDR Memory.
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3. VTT Regulator
It is used to accurately track half of the memory supply voltage VDD while sourcing/sinking the current according to the high/low state of the DDR Memory Bus I/O.
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4. PS Clock Oscillator
33.33 MHz Oscillator was used as a clock source required for ARM Cortex-A9 (PS) operation.
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5. PL Clock Oscillator
50 MHz Oscillator was used as a clock source required for the operation of the FPGA Fabric (PL).
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6. JTAG Connector Footprint
JTAG Connector Footprint was applied for ZYNQ’s program flash and debugging.
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7. Edge Connector (DDR4 SODIMM FF)
Designing the ZYNQ SoC and peripheral circuits for each required system can incur time and financial costs. Therefore, we have adopted the Edge Connector method to allow for the reuse of the ZYNQ and peripheral circuits.
2. Schematic of ZYNQ-7Z010 SOM B’d (Rev.A)
3. PCB Artwork of ZYNQ-7Z010 SOM B’d (Rev.A)
[1] PCB Stack-up based on JLCPCB Impedance Calculation
[2] PCB Layers of ZYNQ-7Z010 SOM B’d (Rev.A)
[3] Delay Matching of DDR Memory
4. Basic Verification of ZYNQ-7Z010 SOM B’d (Rev.A)
1. Check the JTAG Connection Status of the ZYNQ SOM Board
Power the FPGA / SoC B’d and Connect B’d to PC, and Execute Vivado IDE.
And run “Tasks – Open Hardware Manager” to verify that the HW connection is successful before create the project.
As follows, in the case of ZYNQ SOC, Both ZYNQ PS (ARM) and PL should be recognized correctly by Vivado.
2. Test the ARM Cortex-A9 On-chip Memory Read/Write
An additional method to verify the proper connection between the ZYNQ PS and Vivado IDE is to perform Read/Write operations on the OCM (On-Chip Memory) area of the ARM CPU Core.
Run the “xsdb.bat (Xilinx System Debugger)” located at the following path.
Enter “connect” in the console window to connect to the target. This is equivalent to opening the Vivado Hardware Manager and selecting ‘auto connect target’.
This will launch the Hardware Manager as shown below.
Here, by entering “targets,” a list of available targets will appear. You will be able to see the ZYNQ PS (ARM Cortex-A9 Dual Core) and the PL (XC7Z010).
1. Read the data at memory address 0x00001000. (You will see that the data stored at this address is 0.)
2. Write the value 0x12345678 to this address, and then read it again. (You can confirm that the data has been successfully written and read back correctly.)
In this way, you can verify that Vivado and the ZYNQ PS are properly connected.
3. Diagnostics Test for DDR Memory
① Memory Test (1MB, 32MB)
As a result of the test, an Error Count of ‘0’ indicates that the DDR Memory Read/Write operations were performed successfully.
② Read Data Eye Measurement Test
As a result of the Read Data Eye Measurement Test, an Eye Width of over 70% indicates that the performance is very good.
③ Write Data Eye Measurement Test
As a result of the Write Data Eye Measurement Test, an Eye Width of over 70% confirms that the performance is very good.
5. ZYNQ PS Verification Example (LED, SW, TFT-LCD)
1. Verification Items
① GPIO Output → LED Toggling & TFT LCD Control.
② GPIO Interrupt → Tact SW input.
③ UART → Print messages to PC’s Serial monitor.
④ Timer Interrupt → Print messages every 1 [sec] in Interrupt Service Routine.
2. B’d Operation Video
6. ZYNQ PL Verification Example (BRAM Controller AXI IP)
1. Verification Procedure
① Design the “BRAM” module.
② Design the “BRAM Controller” module to Read/Write data to/from “BRAM”.
③ Attach an AXI4 Lite Interface to the “BRAM Controller” to create the “BRAM Controller AXI IP”.
④ Create a Vivado project to test the “BRAM Controller AXI IP” :
Configure the ZYNQ PS, connect the BRAM Controller AXI IP, and generate the Bitstream. Then, export the HW Platform (XSA).
⑤ Create a Vitis project based on the exported XSA file to Read/Write data from/to the “BRAM Controller AXI IP” in the ZYNQ PS.
⑥ Perform basic setup for the Vitis project :
Organize the ZYNQ PS folder structure and add common drivers (gpio, tim, gic, tft_lcd, and user_app). Add the driver paths to the arm gcc compiler/Linker (refer to ‘Vitis Project Initial Setup‘).
⑦ Check the BSP for the HW Platform (XSA) to get the IP information.
(IP Base Address, Register Offset, and Register Write/Read Macro function)
⑧ Design the User IP Driver based on the above IP information.
⑨ Use the User IP Driver to design the IP test code and perform verification of the IP.
2. Timing Diagram of BRAM Controller
When designing an IP, the most important thing is to clearly describe the behavior of the IP.
Additionally, creating a Timing Diagram is the most intuitive and useful method for describing the behavior of the IP.
3. BRAM Controller AXI IP Register Map
The IPs of the PL (Programmable Logic) and PS (Processing System) communicate by reading and writing data to the AXI registers.
Therefore, a register map that details the information for each bit of the AXI register should be documented so that the software engineer can easily use the AXI IP.
4. ZYNQ HW Platform to Verify BRAM Controller AXI IP
Now, to verify the BRAM Controller AXI IP, create a separate Vivado project.
In the Block Design, add the ZYNQ PS and the BRAM Controller AXI IP as follows.
5. ZYNQ PS Code for Verification
To verify the “BRAM Controller AXI IP,” data must be written to and read from this IP in the ZYNQ PS. Therefore, create a Vitis project based on the HW Platform (XSA) file exported from Vivado.
6. Execution result of ZYNQ PS Verification Code
Then, you can verify that the PS data is written to the BRAM Controller IP via the AXI Bus and then read back, as follows.
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